1. Field of the Invention
This invention relates to a low-noise output stage for semiconductor electronic circuits.
More particularly, though not solely, the invention concerns an output stage of the type which comprises a complementary CMOS transistor pair, including a P-channel pull-up transistor and an N-channel pull-down transistor, connected between a first terminal, receiving a supply voltage, of a circuit and a second terminal of the circuit which is held at a second reference potential, said transistors being connected to each other to provide an output terminal for connection to an external load.
2. Discussion of the Related Art
As is well known, electronic circuits which are monolithically integrated on a semiconductor, or chips, are assembled into a package which comprises a case formed from a thermosetting resin and having a lead frame embedded therein for supporting electric connection pins, the electronic circuit having been bonded to the lead frame.
These pins are allowed to project outwards from the resin case, and are bent to form a set of comb-like connectors for plugging into a printed circuit board, for example. On the case inside, the terminals or pads of the electronic circuit are connected to the inner ends of the pins by small interconnection wires, referred to as the bonding wires.
The accompanying FIG. 1 shows, by way of example, a schematic view of a semiconductor chip having terminals A, B, C and D for connection to respective external supply pins.
Terminals A and B are intended for receiving a supply voltage, while terminals C and D are intended for ground connection. Also shown in FIG. 1 are the inner end portions of a first pin H on which a first supply voltage reference Vdd is received and a second pin K on which a second supply reference, such as a signal ground, is received.
Respective connections are provided between the terminals A, B and the pin H which are formed of bonding wires; like connections are provided between the terminals C, D and the pin K.
The bonding wires have an inherent inductance, denoted by L. The dual connections between the terminals A, B and the pin H, or between the terminals C, D and the pin K, are shown in FIGS. 1A and 1B, respectively.
The inductance value between terminals at the same potential and their corresponding pins H or K, is given by the ratio L/2. More generally, calling N the number of the connections made between a given set of terminals at the same potential and one pin, the overall inductance of the bond will be L/N, representing the value of N inductance L in parallel.
The above explanation has been given to introduce the problems which are encountered when an output stage of an electronic circuit is required to change its logic output value.
This is the case, for example, with electronic memory circuits that have a circuit portion for reading the contents of the memory cells. Incorporated within this circuit portion are output stages arranged to change their logic states in order to output the contents of the memory cells.
Many electronic circuits of this type have output stages which incorporate a complementary pair of transistors, e.g. a P-channel MOS pull-up transistor connected to an N-channel MOS pull-down transistor.
This complementary pair forms essentially a CMOS inverter which is connected and powered across the terminal A, at the supply voltage Vdd, and the terminal D, at ground potential.
The circuit interconnection node between the transistors of the complementary pair forms the stage output U. An external load Cload of the capacitive type is usually connected to the output U and is charged or discharged as the voltage at the output stage is switched.
The external load is normally of at least a hundred picoFarads, and for it to be charged or discharged within a reasonable length of time, on the order of tens of nanoseconds, the output stage must be able to supply a relatively large current, e.g. a current of 10 to 15 mA.
During the switching step, either the pull-up or the pull-down transistor will be turned on, resulting in a voltage drop across the bonding wires between the electronic circuit terminal, A or D, and the corresponding one of the pins.
In essence, the nodes A and B "shift" in voltage during normal operation of the circuit; that is, the internal supply voltage Vdd will decrease and the internal ground increase.
The voltage drop causing these variations is tied to the inductance value of the bonding wires by the following relationship: EQU v=L*(di/dt).
Where N output stages are switched simultaneously, e.g. with N=8 for an eight-bit memory circuit or N=16 for a sixteen-bit memory circuit, the above relationship changes to: EQU v=N*L*(di/dt),
which can be re-written as follows: EQU .DELTA.V=N*L*.DELTA.I.
FIG. 2 shows a voltage vs. time plot which illustrates the behaviour of the ground terminal D during the initial simultaneous turning on of eight output stages.
The discharge current of the pull-down transistor causes the voltage at the ground terminal D to rise. A corresponding voltage rise is also induced on the terminal C, which is in turn connected to the pin K but also connected to the terminal D inside the output stage.
Specifically, with reference to the accompanying FIG. 3, it can be seen that the terminals C and D are connected to each other within the circuit by:
a resistance Rsub of the semiconductor substrate P; and PA1 a pair of resistances Rring contributed by the bias rings of the NMOS transistor of the input stage and the transistor Nu of the output stage, respectively.
Through a series of these three resistances, the discharge current of the capacitive external load Cload is passed to the terminal C of the internal ground GNDcore.
Assuming that the input S of the output stage is applied a signal at a logic high, the pull-up transistor will be turned off, and the pull-down transistor turned on. Under this condition, the potential at the terminal D will rise due to the discharge current Idis of the network RLC formed of the resistive, inductive, and capacitive components of the bonding wires.
Such a situation, depicted schematically in FIG. 4, may be a cause of false readings in a memory circuit and the generation of an unwanted ATD (Address Transient Detection) signal that will enable a fresh unwanted reading from the memory cells.
If a fresh reading is enabled, either of two different situations may arise, dependent on the memory address that has been input at the time the switching takes place.
Where the memory address is unchanged, merely a delay would appear in the memory access time; but where the memory address has changed, a fresh cell would be read undesirably.
The underlying technical problem of this invention is to provide a low-noise output stage which has such constructional and functional features as to remove any risk of false readings following a changeover.
This allows the limitations and drawbacks of the output stages for electronic memory circuits according to the prior art to be overcome.